1. Field of the Invention
The present invention relates to a static random access memory (SRAM), and more particularly to an SRAM in which the value of the power supply voltage supplied to memory cells at non-access time is set to be lower than the value of the power supply voltage supplied to the memory cells at access time.
2. Description of the Related Art
Recently, an SRAM is being developed having low power consumption and high performance. Particularly, as an SRAM realizing low power consumption, an SRAM with a row-by-row dynamic VDD (RRDV) controlling method is disclosed, for example, in Kenneth W. Mai et al. “Low-Power SRAM Design Using Half-Swing Pulse-Mode Techniques” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 11, pp 1659-1671, NOVEMBER 1998. In the above-mentioned SRAM of the RRDV controlling method, in raising the voltage of the word line to select one row of a memory cell array, the power supply voltage supplied to the plurality of memory cells within the row is raised to a high voltage. At this time, a low voltage is supplied as a power supply voltage to the plurality of memory cells in the non-selected rows.
In an SRAM, data is latched with a flip-flop circuit disposed within each memory cell. For this reason, a power supply voltage must be supplied at all times to the non-selected memory cells. In an SRAM of the RRDV controlling method, the low power consumption is realized by supplying to the non-selected memory cells a power supply voltage lower than the one supplied to the selected memory cells. However, an SRAM of the conventional RRDV controlling method raises a critical problem in the stability of stored data.
In an SRAM, a precharging period exists before a memory cell is accessed. Namely, before the memory cell is accessed, the bit line connected to the memory cell is precharged to a high potential. This precharging process is carried out usually with the use of a high voltage which is the high power supply voltage supplied to the memory cell.
On the other hand, the power supply line which supplies the power supply voltage to the memory cells and the word line which selects the memory cells each have a certain degree of wiring length, whereby a signal delay occurs in correspondence with a parasitic capacitance and a parasitic resistance associated with each. Moreover, the delay time in the power supply line may not be the same as the delay time in the word line. Therefore, it may not happen that, at the time of accessing a memory cell, at all the positions of the power supply line and the word line, first the voltage of the power supply line rises to the high voltage, and then the voltage of the word line rises to the voltage corresponding to the selected state and, at the time of non-access to the memory cell, first the voltage of the word line falls to the voltage corresponding to the non-selected state, and then the voltage of the power supply line falls to the low voltage. Therefore, in an SRAM of the conventional RRDV controlling method, during the precharging period in changing from the non-access state to the access state, the word line voltage may be raised to be high before the power supply voltage supplied to the memory cells is raised.
FIG. 1 shows one example of the relationship between a static noise margin (SNM) of a memory cell in a non-selected state and the word line voltage in an SRAM by a conventional RRDV controlling method. Here, the value of the power supply voltage VDDL supplied to the memory cells in the non-selected state is, for example, 0.25V. FIG. 2 shows one example of the voltages Vin, Vout (Vin and Vout are voltages of the storage nodes N1, N2 of a later-mentioned flip-flop circuit of FIG. 4) at one pair of input and output nodes of a flip-flop circuit within a memory cell when the voltage of the word line is set to be 0.00, 0.25, and 0.30V. Here, the characteristics shown in FIG. 2 are generally known as a Butterfly curve. SNM1, SNM2, and the like in FIG. 2 correspond to SNM of FIG. 1.
As will be clear from FIGS. 1 and 2, when the word line voltage rises in a non-selected memory cell to which the low voltage is supplied as a power supply voltage, the static noise margin decreases, thereby inconveniently leading to destruction of the cell data.